The present invention relates to metal gate formation, and more specifically, to metal gate formation on replacement metal gate fin field effect transistor (finFET) devices.
Generally, a replacement metal gate (RMG) process architecture is a gate last versus a gate first architecture. RMG finFET device fabrication typically includes initially forming a dummy gate structure that is subsequently removed to form a gate pocket after spacer etch and source/drain epitaxy merge. A high dielectric constant (high-k) layer, work function metal, and gate metal are filled into the gate pocket, and chemical-mechanical planarization (CMP) is performed to planarize the topology. The gate metal material is then recessed partially and a dielectric cap is formed through damascene processing.